Features
- Two 215−MHz, 12−bit A/D converters
- RF transformers supports 700 MHz input
- Four FPDP front panel outputs
- FIFO buffering for real−time recording
- Advanced Xilinx® Virtex−IV FPGAs
- Multi−board synchronization
Specifications Front Panel Connectors
- Analog Inputs: Two female SMA connectors
- Sample Clock Input: One female SMA connector
- Sync/Gate Bus: One 26−pin connector, with four gates, one sync, and one clock input/output LVDS signals, plus one sync and one gate input TTL signals
- FPDP Outputs: Two 80−pin FPDP connectors (A and B)
- FPDP Outputs: Two 80−pin FPDP connectors(C and D)
Analog Signal Inputs
- Quantity: 2 Front panel SMA connectors
- Input Type: Single−ended, non−inverting
- Coupling: AC
- Input Impedance: 50Ω
- Full Scale Input: + 8dBm (1.59 Volts p−p) or +2 dBm (0.796 Volts p−p)
Analog Input Transformers
- Quantity: 2
- Type: Mini−Circuits ADT1−1WT
- 3 dB Passband: 400 kHz to 800 MHz (limited to 700 MHz by A/D)
Analog/Digital Converters
- Quantity: 2
- Device: Analog Devices AD9430
- Sampling Rate: 60 MHz to 215 MHz
- Resolution: 12 bits
- Bandwidth: 700 MHz at full power
- Coupling: Transformer coupled
- Clock Source: On-board crystal oscillator or external clock
- Internal Clock Frequency: 210−MHz crystal oscillator (standard) 213.333−MHz crystal oscillator
- External Clock Input Source: Front panel SMA connector
- Type: Single−ended, non−inverting, Sine Wave
- Frequency: 60 MHz to 215 MHz
- Impedance: 50Ω, AC coupled
- Full−scale Input Voltage: 0 to +4 dBm
External Sync/Gate Inputs
- LVDS Signals: Front panel LVDS Sync Bus inputs/outputs:
- GATE A: 2 LVDS pins (1 differential pair)
- GATE B: 2 LVDS pins (1 differential pair)
- GATE C: 2 LVDS pins (1 differential pair)
- GATE D: 2 LVDS pins (1 differential pair)
- FPGA SYNC: 2 LVDS pins (1 differential pair)
- CLK: 2 LVDS pins (1 differential pair)
- TTL Signals: Front panel TTL inputs:
- TTL GATE: 1 pin
- TTL SYNC: 1 pin
- Gate Disable: Each gate can be disabled; when disabled, FIFO writes default to enabled
- Triggering: Each gate can be programmed as a trigger
Field−Programmable Gate Arrays
- Quantity: Two Products – 2011 22 / 57
- Device: Xilinx Virtex−IV XC4VFX60,Xilinx Virtex−IV XC4VSX55
- Programming: Factory programmed.
Memory
SDRAM
-
- Quantity: Two, one per FPGA
- Size: 256 MBytes (32M x 32) each
- Note: Each FPGA bank contains four 16M x 16 chips, configured for a 32−bit wide data bus
- Interface: Interfaced to FPGA
Flash
-
- Quantity: Two, one per FPGA
- Size: 16 MBytes each
- Mapping: Programmable by the corresponding FPGA
- Write Enable: With jumper
Additional Flash
-
- Quantity: Two, one per FPGA
- Size: 32 MBits each
- Mapping: Programmable by the corresponding FPGA
Digital Outputs
- Quantity: Standard: Two Front Panel Data Port (FPDP) connectors, each providing 32−bit output
- Output Type: FPDP I, non−inverted configuration FPDP II, double the selected clock rate
- Clock: On−board clock
FIFOs
- Quantity: Four IDT72V3690 FIFOs, one for each FPDP port
- Size: 32,768 x 36
- Speed: FIFOs are capable of 166 MHz speed, but are run at one half of sample clock speed
VME Slave Interface
- Type: Slave A.64 D64, A64/D64
- Control: Operating modes, gate/trigger, FIFO reset, data packing, FPDP I or II, FPDP framing, time sync command and status (read only)
Environmental − Commercial Applications
- Operating Temperature: 0° to 50°C
- Storage Temperature: −20° to 90°C
- Relative Humidity: 0 to 95% non−condensing
- VME Rack Exhaust Temp: 0° to 50°C
- Environmental − Ruggedized Applications Cooling Method (operational): Forced Air
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